A. Technical Field
The present invention relates to the communication of storage request commands, and more particularly, to providing a plurality of communication modes in which variable request size commands are communicated between a controller and a host system.
B. Background of the Invention
A host processor or device driver communicates with various peripheral devices to control the operation of these devices within the processor's system. One such example is a processor communicating with a memory device, such as a redundant array of independent disks (“RAID”), via a PCI Bus. A controller within the RAID may receive a request, such as a read/write command, from an operating system and perform a corresponding action on one or more drives within the RAID. Typically, this communication between the operating system and memory device occurs in fixed length words that are defined within the system so that both operating system and the controller communicate properly.
One such example is the use of a 32-bit word, sent during a single input/output cycle, in which an address may be provided relating to a particular request. This particular example presents a problem if the system memory size requires a word that is longer than 32-bit in order to communicate a physical address. This problem is currently addressed by effectively patching a longer address within the 32-bit word using standard coding techniques. The encoded address is sent to the controller, which must extract the address using decoding techniques.
This method of communicating coded addresses within a 32-bit word still limits the maximum addressable memory due to the limited amount of information that can be stored in 32-bits. Another common solution is to simply increase the size of the passed address to 64-bits. This option allows addressability of the full address space of today's computer systems, but has the disadvantage or requiring two 32-bit 10 cycles in order to communicate the 64-bit address. The primary disadvantage with this approach is that it effectively requires multiple cycles in order to communicate the address to the controller. In particular, the process requires double buffering within a 32-bit address buffer, reading this buffer, and extracting the actual address. This overhead occurs for all addresses, even those that do not require 64-bit addressing. The process introduces inefficiencies within the fetching operations and causes delay in the performance of requests.
Accordingly it is desirable to provide a device and method that addresses the above-described problems.